Reed Solomon FEC Codec
Softnautics Reed Solomon IP core codec is based on IEEE 802.3bj Clause 91 specification. Cyclic code used is RS (528,514) for 7 symbol error correction and RS (544,514) for 15 symbol error correction. Encoder and Decoder are separate synthesizable cores.
Flow-through design with low latency
Different architectures available to meet area and throughput requirements. RS based IP cores available for applications beyond IEEE 802.3bj.
- RS (544,514) and RS (528,514) can be switched dynamically i.e. code word by code word
- Parallel interface for processing multiple symbols in a clock
- Ability to bypass error correction to reduce latency through the core
- Small FIFO inside the core to store the code word while it is being decoded
- No memory required
