Softnautics xSPI Verification IP


Softnautics xSPI Verification IP provides verification of xSPI (Extended SPI) for devices using the Serial Parallel Interface (SPI) protocol for master and slave modes. It is a reusable, configurable, pre-verified, and plug-and-play verification component developed in System Verilog.

JESD216 protocol with multi-thread logic

Softnautics xSPI VIP supports a comprehensive set of protocol, methodology, verification features to help accelerated verification closure of SPI Bus and Flash-based designs. It can be seamlessly integrated with the protocol-aware debug environment to provide operations, transactions, and memory content view for fast and efficient debug.

  • JESD 251 compliant Protocols 1 & 2
  • Support flexible erase options (4/8/32/64KB block erase)
  • Flexibility – Single VIP supports multiple SPI protocols
  • Plug-and-play integration with most SoCs
  • Allows backdoor read/write access to Mode Registers and Device Memory
  • Dynamic modification of timing parameters

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