Design Verification Engineer

Job Description

Softnautics is Silicon Valley based semiconductor and embedded AI solutions company with design expertise in systems software, FPGA, and VLSI IP development. We continue to grow and develop our team to ensure we maintain our position going forward. To do this we need to recruit high caliber resources with the skills that matter most to Softnautics which differentiate us from our competition. Softnautics requires skilled verification engineer who is confident, self-motivated and has strong fundamentals. The successful candidate will be responsible for VE architecture, implementation level documentation, SV/VUM coding, test-plan development, assertion and functional coverage coding, simulations and related activities. The candidate is required to have the skills to train junior resources. The role will be part of the VLSI group function in which there is a very strong culture of teamwork, cooperation and collaboration for common goal of producing quality deliverables.


  • Understand the standards/specifications
  • Architecture development and documenting implementation level details
  • Hands on work for every aspect of verification cycle
  • Responsible for the compliance with the latest Methodologies.
  • Developing Verification IPs
  • Define Functional Coverage matrix and Comprehensive Test plan
  • Regression management and functional coverage closure
  • DUT integration and verification for IP delivery sign-off
  • Leading small team

Skill Set

Required Skills

  • Hands-on experience of complete verification cycle with strong verification concepts
  • Strong knowledge of Verilog, SystemVerilog and UVM
  • Experience in UVM based Verification IP development
  • Experience in AMBA AXI/AHB/APB System buses
  • Hands on work experience on any of PCIe/Eth/USB/DDR etc.
  • Hands on experience with System Verilog Assertions
  • Scripting for automation, release process, simulations, regressions
  • Good command over written and oral communication

Desired Skills

  • Lead the Verification IP development with 2 or more junior engineers
  • Exposure to full verification cycle
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