Get high-quality
IP Solutions that deliver
results with precision
At Softnautics, we consider overall customer success when we design and implement our IP
solutions. We work proactively in high-speed serial, security, and codec technology areas to deliver semiconductor design IPs and provide ASIC/FPGA front-end services.
USB3.2 IP is designed for applications requiring USB3.x Host or Device or Dule Role Device (DRD) implementation
It is USB3.x compliant with Gen2 x2 with fallback support for Gen2 x1, Gen1 ×1, and USB2.0 speed modes over Type C or standard USB Host/Device connectors
USB3.2 IP is designed for applications requiring USB3.x Retimer implementation
It is USB3.x compliant with Gen2 x2 with fallback support for Gen2 x1, and Gen1 ×1 speed modes over Type C or standard USB Host/Device connectors
AES core implements Rijndael algorithm for encryption and decryption of plain text using cipher keys
• Fully synchronous design
• Supports AES 128 and AES 256 in various modes
SHA-1 IP core implements Secure hash algorithm specified in FIPS available for ASIC and FPGA applications
• 64 bit or 128 bit data path interface
• Message size supported is 2^64 bits and is divided into 512 bit blocks
Reed Solomon IP core codec is based on IEEE 802.3bj clause 91
• Ability to bypass error correction to reduce latency through the core
• Multichannel and backpressure for decoders
Erasure IP consists of a separate encoder and decoder synthe-sizable cores and FPGA apps
• The IP accepts customizable parameters and uses non binary, cyclic, linear block error correction code to solve the issue
• No additional memory is required for the encoder
