USB3.2 ReTimer Core


This ReTimer Controller softcore semiconductor-IP is designed for USB3.2 SuperSpeedPlus and SuperSpeed USB-Retimer implementations. The core is optimized for low power requirements.

The core is highly power efficient for port or cable retimer applications

Softnautics USB3.2 Retimer softcore is designed for use USB Port/Cable Retimer applications with USB SuperSpeedPlus/SuperSpeed link operations. The IP has been verified in simulation and is synthesis clean for FPGA implementations.

  • SuperSpeedPlus @10Gbps with fallback to SuperSpeed @5Gbps
  • USB-Link parallel data-path 20bit for SS, and 32bit for SSP
  • Implements Digital-PHY PCS as part of the core supporting 8b/10b and 128b/132b codec with scrambler and descrambler, error detection-correction, Clock offset compensation with elasticity buffer, LFPS, full LPM, and compliance-mode
  • Easy customization for interface to PMA/SERDES logic and sideband signaling

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