Soft Error Mitigation Library
The client is US based leading semiconductor company offering FPGA, programmable SoCs, and Adaptive Compute Acceleration Platform. With dynamic processing technology and advance tools, they drive rapid innovation across a wide span of industries and technology domain, from consumer to cars to the cloud.
The client approached Softnautics to design and, develop the Soft Error Mitigation (SEM) library on BareMetal at Boot level and validate the same for Versal ACAP platform.
Softnautics played a significant role in developing the Soft Error Mitigation (SEM) Library to perform SEU detection, correction, and classification for configuration memory. The error injection feature provides a means to evaluate and test the SEU mitigation capabilities of the IP cores without the need for expensive test time at a radiation effects facility.
80% memory footprint optimization
63% increased performance in NPI Scan including complex hardware designs
95% increased performance in CRAM Scan to detect bit flip errors