SHA-1 IP core implements Secure Hash Algorithms specified in FIPS 180-4 standard. Common cores are available for ASIC and FPGA applications.
SHA1 64/128 Crypto Core
Fully synchronous design
Softnautics core supports higher frequency andaccepts data every 41 or 21 clocks as opposed to every 80 clocks for IP’s available in the market.
- SHA1 supports SHA1 as per FIPS 180-4
- 64-bit or 128-bit data path interface
- Padding is added as per the specification to make message a multiple of 512-bit block
- SHA1 produces message digest of 160 bits
- Accepts new block every 41 clocks (64-bit data path) or 21 clocks (128-bit data path)