JTAG Verification IP
Softnautics JTAG Verification IP is reusable, configurable, pre-verified, and plug-and-play verification component. It provides a comprehensive set of protocols, methodologies, and verification features to achieve rapid verification of designs using JTAG. It is developed in System Verilog.
JESD216 protocol with multi-thread logic
Softnautics JTAG is a comprehensive solution that can run natively on any IEEE compliant simulator to gain optimum performance. It supports Universal Verification Methodologies (UVM) and legacy methodologies through a unique flexible architecture.
- Support JTAG Protocol Standard – IEEE 1149.1-2013
- Support user-defined instruction and data-registers
- Configurable instruction registers and data register width
- Dynamic configuration for data register width
- In-built verification plan to map functional coverage to the protocol specification