Verification Engineer VLSI


  • Softnautics requires skilled verification engineer who is confident, self-motivated and has strong fundamentals. The successful candidate will be responsible for spec understanding, VE architecture-implementation, documentation, SV/VUM coding, test-plan development, assertion and functional coverage coding, simulations and related activities. The candidate is required to have skill so train junior resources
  • The role will be part of the VLSI IP group function in which there is a very strong culture of teamwork, cooperation and collaboration for common goal of producing quality IP


  • Understand the standards/specifications
  • Architecture development and documenting implementation level details
  • Hands on work for every aspect of verification cycle
  • Responsible for the compliance with the latest Methodologies
  • Define Functional Coverage matrix and Comprehensive Test plan
  • Regression management and functional coverage closure
  • DUT integration and verification for IP delivery sign-off

Person Specification

Required Skills & Experience:

  • 4+ years of experience in the relevant field
  • Hands-on experience of complete verification cycle with strong verification concepts
  • Verilog, SystemVerilog and UVM expertise
  • Experience in any Processor based system, SoC, AMBA System bus and DMA concepts
  • Hands on work experience on any of DDR/PCIe/Eth/USB/SATA/DP/HDMI/MIPI etc.
  • Scripting for automation, release process, simulations, regressions
  • Good command over written and oral communication

Desirable Skills:

  • Lead the DUT-verification phase with 2 or more junior engineers
  • Experience in FPGA based pre-silicon verification