Design Verification Engineer


Softnautics is acknowledged as niche product engineering solutions company with expertise in IP Solutions and Embedded Software. We continue to grow and develop our team to ensure we maintain our position going forward. To do this we need to recruit high calibre resources with the skills that matter most to Softnautics which differentiate us from our competition.

Softnautics requires skilled verification engineer who is confident, self-motivated and has strong fundamentals. The successful candidate will be responsible for Spec understanding, Verification Environment architecture-implementation, documentation, SV/UVM coding, test-plan development, assertion and functional coverage coding, simulations and related activities. The candidate is required to have skills to train junior resources.

The role will be part of the VLSI IP group function in which there is a very strong culture of teamwork, cooperation and collaboration for common goal of producing quality IP


2+ Years


  • Understand the Standards/Specifications
  • Contribute in architecture development, documentation, and test-plan
  • Ensure RTL is bug-free by creating and updating Verification Environment, Test-cases, Coverage Coding, Assertions, running Simulations, debugging failures, launching Regressions, etc.
  • Responsible for the compliance with the latest Methodologies
  • DUT integration and verification for IP delivery sign-off


Minimum Qualifications:

You should have bachelor’s degree in Electronics Engineering, Electrical Engineering, Computer Engineering or related field with 2 years of work experience in the field.

Your experience should be in the following areas:

  • Background in logic design, architecture, and logic verification
  • Strong background in Pre-Si validation, Verilog, System Verilog and verification methodologies (OVM/UVM)
  • Proficiency in UNIX and Windows
  • Experience with programming / scripting languages like Python, Perl, C/C++
  • Skills pertaining to logic design and validation, including expertise in a design simulator, functional coverage concepts and implementation, testbench development, bus functional models, trackers, checkers, test development, execution, and debug

Preferred Qualifications:

  • Hands-on experience with strong HVL verification concepts
  • Practical and working knowledge of Verilog, System Verilog and Verification Methodologies OVM/UVM
  • Experience in building testbenches, building and incorporating validation components for stimulus generation & error reporting
  • Practical knowledge of SV assertions and Coverage coding
  • Experience in any Processor based system, SoC, Standard Bus Protocol – AMBA/AXI/OCP and DMA concepts.
  • Hands on work experience on any of Industry standard protocols will be an added advantage: DDR/LPDDR/PCIe/Ethernet/USB/SATA/DP/HDMI/MIPI etc.
  • PERL/PYTHON Scripting for automation, release process, simulations, regressions
  • Experience with Tools like VCS/Verdi/ Incisive/JasperGold / Xcellium /DVE/ simvision /Mentorgraphics Questasim for debug

Desirable Skills:

  • Good command over written and oral communication
  • Exposure to full verification cycle